Pre-processing Solution for 3G LTE Basestation Design

By: Wilson Oon and Jorg Kohlschmidt, Xilinx Inc.
( 1 Jan 2009 )

The Long Term Evolution (LTE) Cellular Standard is one of the two components of 3GPP 3G Evolution, the other being HSPA evolution. The major goal of the LTE is to meet the needs of wireless customers over a period of 10 years beyond UMTS. This includes reduction in usage cost for users and operators as well as providing better services and increase data rate with lower latency.

Better services in the form of service differentiation would be achieved via link adaptation based on QOS concept in both time and frequency domains. On data rate, a peak Downlink (DL) rate of at least 100Mbps and peak Uplink (UL) rate of 50Mbps, giving a spectrum efficiency of 5bps/Hz and 2.5bps/Hz, respectively, are expected. Lower latency is achieved via a flat Network Architecture that is IP based and shorter PHY processing time, besides having the upper layer functions implemented in the eNodeB (eNB) of the LTE.

KEY ELEMENTS OF LTE
LTE Radio Access will be based on Single Carrier FDMA (SC-FDMA) for UL. The adoption of SCFDMA for UL is motivated by the good Peak to Average Power Radio (PAPR) of the SC-FDMA waveform. With lower PAPR, higher efficiency RFPA operation can be attained leading to longer battery life in the handset. For DL, classical OFDMA scheme is adopted.

Apart from the modulation, another key element is the availability of Channel Condition dependent scheduling. This allows time-frequency resource in the shared channel to be shared dynamically between users. The scheduling interval is based on a time division of 1ms and a frequency division of 180kHz. As such the implementation of the Scheduler within the MAC layer is the key element for DL performance as it determines the rate to be used for each link. Like HSDPA, Hybrid ARQ, which resides in the MAC layer, with multiple parallel stop-and-wait ARQ processes and soft combining will be used. The Hybrid ARQ scheme is based on Incremental Redundancy (IR) for retransmission. Besides the above key areas, LTE will have Multiple Antennas support as an integral part of the specification. Receive and transmit diversity schemes, beamforming and spatial multiplexing would be supported.

One of the goals of the LTE system is that it would need to allow for flexible 2G/3G migration to LTE. As such, flexible spectrum allocations spanning 1.25MHz to 20MHz would be available, and the LTE system should be able to operate between 450MHz to 2.6GHz.

KEY ELEMENTS OF THE LTE PHYSICAL LAYER
LTE offers two types of frame structure based on a radio frame of 10ms using common OFDM radio access technologies. The two types of frame structure, namely, FDD/Half FDD, known as Type 1 and TDD known as Type 2, are both based on a 10ms radio frame, with each radio frame having 20 slots of each 0.5ms. The Type 2 frame structure is provided for co-existence with TD-SCDMA.

Central to the ability of LTE systems to offer link adaptation in both time and frequency domain is the use of OFDMA scheme for DL. This means that the DL physical resource is defined in terms of one OFDM subcarrier and one OFDM symbol period; this is known as Resource Element (RE). A total of 84 RE would constitute one Resource Block (RB) which consists of 12 subcarriers over a period of 1 slot (0.5ms) having 7 OFDM symbols. As such the DL transmission signal is defined in terms of resource grid (RG) with 2 REs for each user corresponding to two slots (1ms).

HIGHLIGHTS OF LTE BASEBAND PROCESSING
The DL Physical Layer for Tx and Rx is depicted in Figure 1. Notice that it can be broken down into two types of processing, namely, symbol rate and sample rate processing. It can be seen that the symbol rate processing is simpler compared to UMTS standard based on WCDMA. As in UMTS, the challenges for LTE basestation design lie in the UL processing. In the case of LTE, this is further compounded by the small processing time requirement in order to achieve lower latency in tandem with having higher layer functionality located in the Node B as opposed in RNC.

On a micro level, specifically with respect to the UL signal chain as depicted in Figure 2, the LTE delay budget is mainly defined by the HARQ roundtrip delay of 8ms, i.e. the time between the original and the retransmission. Taking a transmission time of two times 1ms into account, just 6ms are left for the sending and receiving data. That means LTE Uplink processing has to contend with the delay budget of 3ms posed by the following functionalities, namely:
• channel estimation delay
• demodulation
• rate matching and IR combining
• turbo decoding
• MAC/RLC processing
• UL/DL time offset

Given the short processing time required, it is therefore essential that the important modules such as DFT used in SC-FDMA demodulation and Turbo decoding needs to be done in the shortest time possible.

Of greater impact to meeting the UL processing requirement, one has to look at the macro level of basestation design, namely, how to partition the baseband design of the basestation. Currently, basestation vendors could use FPGA as co-processor to perform Turbo decoding to meet the throughput requirements. Other blocks of interest such as the iDFT or RACH preamble detections are illustrated in Figure 3.

However, there is a challenge here due to the delay caused by the interconnect between the FPGA and DSP. We will demonstrate with an UL example based on the commonly used SRIO interface, having the following parameters:
• 10MHz bandwidth, short CP, single sector
• No retransmission
• 4 HARQ processes
• No spatial multiplexing
• Turbo decoding duration based on estimations
• SRIO: 3.125Gb, 1x lane, 8/10 coding, 25 bit overhead per picketer
• Transfer time for DDR2 Memory, 200MHz, 32 bit read only

Various service examples, far from worst case scenarios, were calculated as illustrated in Table 1, including the decode time and the delay for SRIO transmissions which must not exceed a sum of 1ms.

From roll 5 of Table 1, we can summarize that significant delay is incurred in SRIO transfers; and parallel implementation of Turbo decoding is needed.

The major issue here is that latency and data rate requirements posses a challenge in Co-processing approach using single SRIO link, notably, because it incurred a delay of up to 400 us for the case of 20MHz bandwidth which is already 40 percent of the available processing time.

To resolve the delay issue, it would be better to use a Pre-processing approach that is based on FPGA as opposed to a Co-processing approach. This implies that the complete PHY layer processing would need to be done in the FPGA with DSP processor acting as the controller and doing the higher layer functions. This is illustrated in Figure 4. With a Pre-processing approach to the DSP, the DSP would replace the Network processor or reduce the Network Processor function to do centralized PDCP processing and backhaul interfacing. Another advantage of using such approach is that the FPGA could be used for MAC acceleration function to compensate the low control code performance seen on DSP. The other approach is to use FPGA as pre-processor to Network Processor as depicted in Figure 5.

As a whole, these two approaches yield several advantages besides overcoming the delay issue, such as making provision for specification changes along the way.

XILINX LTE BASEBAND REFERENCE SOLUTION
Xilinx recently demonstrated a LTE Baseband DL solution for PDSCH that is 3GPP LTE compliant at Mobile World Congress 2008 held in Barcelona. The reference solution consists of the relevant Xilinx LTE IP cores that include Turbo Encoding/Decoding, Rate Matching, FFT/iFFT with Cyclic Prefix Insertion, QAM Mapper and Demapper. The DL Transmit and Receive Chains of the reference solution are depicted in Figure 1. This reference solution also serves to provide a system level validation of the developed IP cores for LTE [3].

A successful demonstration of well above 100Mbps of streaming video over 10MHz bandwidth was conducted. The successful demonstration uses a reference application for video-streaming based open source VideoLan Server which runs on a host PC. The LTE baseband reference solution sits on two recently launched ML507 board. This is illustrated in Figure 6.

REFERENCES
[1] 3GPP TS 36.104 V8.0.0 (2007-12), EUTRA Basestation Radio Transmission and Reception.

[2] "Technical Solutions for the 3G Long-Term Evolutions", Hannes Ekstrom, et al., IEEE Communication Magazine, March 2006.

[3] "Implementing the Next Generation of Wireless Standards using Virtex-5 FXT", Rob Payne, Xilinx Xcell Magazine, 2008.

[4] "3G Evolution, HSPA and LTE for Mobile Broadband", Erik Dahlman, et al.,ELSEVIER, 2007.

[5] "Single Carrier FDMA for Uplink Wireless Transmission", Hyung G. Myung, et al., IEEE Vehicular Technology, Magazine, September 2006, page 30.

CAPTIONS
Figure 1: 3GPP LTE DL processing.
Figure 2: LTE UL signal chain.
Figure 3: FPGA as coprocessor for LTE.
Figure 4: FPGA pre-processing with DSP architecture.

Click here for the illustrations:

Figure 1, Figure 2, Figure 3, Figure 4, Figure 5, Figure 6, Table 1