Complete Digital Front-end Design Accelerate Development of 3GPP LTE Radios for Wireless Base Stations

(Top News, 18 Dec 2008)

Xilinx Inc. has released a complete Digital Front End (DFE) design optimized for faster, lower cost development of 3rd Generation Partnership Protocol (3GPP) Long Term Evolution (LTE) wireless communications systems. It is said to be the industry's first DFE design specifically targeted for high performance 3GPP LTE radio applications that reduces overall power consumption and is scalable from large multi-sector macrocell to picocell base stations.

The Xilinx 3GPP LTE design supports a fully featured programmable development platform using Xilinx Virtex-5 FPGAs. The LTE DFE platform consists of highly optimized blocks for Digital Up Conversion (DUC), Digital Down Conversion (DDC) and Crest Factor Reduction (CFR) that together form a complete LTE radio subsystem. It is compatible with existing Digital Pre-Distortion (DPD) designs from Xilinx, enabling systems architects to rapidly develop and integrate all the digital system elements of a high performance, commercial LTE system, and in a significantly shorter period of time than is feasible with traditional application-specific standard part (ASSP) and application-specific integrated circuit (ASIC) design methods, of which there are none currently available supporting LTE systems.

The LTE DFE design is highly configurable and has been architected to support seven single- and multi-carrier implementations, including: single carrier 5, 10, 15, and 20MHz bandwidths; dual carrier 5 and 10MHz bandwidths; and four carrier 5MHz bandwidth. With optimized solutions provided for each configuration, designers can select an implementation based on their system requirements, without paying a penalty on design area and helping to reduce overall system cost and power. Using the Xilinx System Generator for DSP tool suite, the design also can be easily customized to meet the needs of company-specific 3GPP-LTE radio applications.

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