Altera Releases Quartus II Software Version 8.1

(Product News, 5 Nov 2008)

Altera Corp. has unveiled Quartus II software version 8.1, the latest release of Quartus II software, which continues the company's history of delivering high-density FPGA compile times three times faster than other FPGA-vendor supplied development software, based on internal benchmarks. The enhanced productivity features within Quartus II software enable design teams to close timing and power faster, lower R&D costs and shorten time to market.

While next-generation FPGAs deliver a greater level of functionality, design teams continue to be constrained by limited development times. Quartus II software version 8.1 helps speed development times by automating traditionally time-consuming features. The design partition planner, introduced in the previous version of Quartus II software, now provides automated partitioning in version 8.1, allowing more designers to leverage the productivity benefits of incremental compilation. Quartus II software now also eliminates the need to modify gated clocks manually by automatically converting gated clocks to functionally equivalent logic supported by the FPGA architecture. Automating these features allows design teams to focus more effort on value-added portions of the design.

Other key features of Quartus II Software Version 8.1 include:
• SignalTap II Embedded Logic Analyzer
Finer data-sampling control speeds debugging and improves on-chip memory efficiency.

• Enhanced SOPC Builder Tool
- New HDL templates enhance the speed and ease for which SOPC Builder can be used for intellectual property (IP) reuse.
- A new Avalon memory-mapped half-rate bridge is available for low-latency access for DDR SDRAMs.

• New operating system support ¨C Red Hat Enterprise Linux 5 and CentOS 4/5 (32 bit/64 bit) are now included.

• Enhanced third-party simulation interface
The interface supports automatic compilation of library files for faster simulation setup.

• New Pin-Out Advisor
The advisor guides pin-out creation and interface with third-party board tools.

• Real Intent Verification Support
Real Intent's Meridian FPGA Clock Domain Crossing (CDC) software offers easy-to-use automatic clock intent verification to catch design errors and create confidence in reliable CDC operations.

• New and enhanced IP cores and megafunctions
Digital signal processing (DSP), memory and protocols accelerate development.

• Physical synthesis engine enhancements
Improve performance of timing-critical blocks in 20 percent less time on average than the previous version for faster timing closure.

• Synopsys Design Constraints (SDC)
SDC templates guide and accelerate timing constraint creation.

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