Crest Factor Reduction in Multi-carrier Base Station Application

By: Wilson Oon, PhD, SMIE, Xilinx Asia Pacific Pte Ltd
( 1 May 2008 )

This article presents Xilinx Inc.'s latest reference solution for Crest Factor Reduction known as Peak Cancellation CFR (PC-CFR). This paper will first start by reviewing the motivation for using CFR technique in relation to RFPA efficiency. This is followed by a brief review of the various CFR techniques, inclusive of performance comparison between the various schemes when applied to Multi-Carrier TD-SCDMA standard. FPGA resources requirement for implementing a specific TD-SCDMA Multi-Carriers system configuration will also be discussed.

CREST FACTOR AND RFPA EFFICIENCY
Power efficiency of an RFPA (RF power amplifier) is of prime importance in cellular radio basestation design given its significant impact on OPEX and CAPEX. High efficiency RFPA solutions lead to lower CAPEX as smaller power amplifier can be used for the same desired output power or less cooling infrastructure is needed. On the other hand, it also leads to lower OPEX as less power is consumed.

The need for higher efficiency in the RFPA has lead to the evolution of basestation architectures from passive combination of single carrier power amplifier (SCPA) outputs to that of digital combination of carriers at IF based on multi-carrier power amplifier (MCPA) approach. The latter approach also allows the application of crest factor reduction (CFR) technique and digital linearization technique such as digital pre-distortion (DPD).

However, linear combination of carrier signals leads to high Peak-to-Average Power Ratio (PAPR). This applies not only to 3G CDMA carriers but also applies to multi-carrier EDGE and GSM signals. Even single carrier CDMA or OFDM signal exhibits high crest factor (CF) due to linear combination of independent waveforms in the generation of individual CDMA and OFDM carriers.

While CF is used to measure PAPR and can be defined and given by equation (1),



where x is a real valued up-converted bandpass signal.

High CF requires that the commonly used Class AB RFPA be operated at a certain Output Back Off Level in order to prevent the high peak signal from driving the RFPA into nonlinearity. Let us first examine what is the relationship between CF and RFPA efficiency.

RFPA efficiency is defined as average output power to the DC power supply based on certain operating point, as given by equation (2).



This implies that to achieve higher efficiency, the RFPA output should be driven close to the saturation point (beyond which non-linearity effects will kick in). However, in actual operation, the output power is back off not only to account for the CF of the input signal to the RFPA but also to account for other weak nonlinearity in the RFPA.

Figure 1 illustrates the relationship between Input Power Back Off (IPBO) and Output Power Back Off (OPBO). OPBO is defined as the ratio of maximum output (saturation) power to actual output power. To achieve the desired OPBO level, the IPBO has to be increased. Since the operating point remains the same, the denominator in Equation will remain the same but the numerator will decrease with larger OPBO resulting in decrease in efficiency.

There are two ways to resolve the reduced efficiency with increase OPBO in view of the high CF of the signal. One can use an effective CFR scheme to reduce the PAPR of the multi-carrier input signal or use DPD to extend the range of linear operation of the RFPA. By reducing the PAPR of the combined input signal to the RFPA, the IPBO can be reduced which then leads to lower OPBO and hence obtaining efficiency improvement.

With CFR, typical efficiency of around 16 percent can be achieved compared to 8 percent for the case where CFR is not used.

CFR TECHNIQUES
To date, many CFR schemes have been proposed ranging from Codes Selection, I & Q or Polar Clipping at Baseband, Peak Windowing CFR (PWCFR), Noise Shaping CFR (NS-CFR) and Pulse Injection CFR (PI-CFR) [4].

Xilinx has recently introduced a technique known as Peak Cancellation CFR (PC-CFR), which is shown to perform better while at the same time uses less resources due to reduced computational burden besides other advantages [3].

Peak Windowing CFR (PW-CFR)
PW-CFR, which is an extension of conventional clipping technique, provides PAPR reduction by applying time domain scaling to the clipped signals.

The equation for convention clipping is given by the following equation [6],



where c(n) is defined in the following equation where A is the maximum amplitude allowed for the clipped signal. The idea is to replace c(n) with a smoother function b(n) using suitable window in order to limit spectral spreading of the clipped signal,



The ACLR and EVM performance of the PWCFR processed signal, y(n) is dependent on the type of Window used and the length of the Window [6]. Window length provides a trade off between ACLR and EVM performance, longer Window provides better ALCR figure at the expense of degraded EVM performance.

Noise Shaping CFR (NS-CFR)
This scheme is first offered by Xilinx as a reference solution for WCDMA Digital Front-End [2] and subsequently for WiMAX. NS-CFR provides CF reduction by cancelling all the samples that exceed a certain clipping threshold.

In an NS-CFR system, conventional polar clipping is employed to clip the signal peak above certain threshold. The clipped signal is then noise shaped to ensure that the noise arising from the clipping action falls within the signal band.

The noise shaped clipped signal is then used to cancel from the original signal to provide the PAPR reduction. Peak re-growth can arise from the process described above which further iteration of the scheme can be used in subsequent stages to mitigate it. NS-CFR scheme offers better performance compared to PW-CFR.

Pulse Injection CFR (PI-CFR)
A PI-CFR scheme is usually employed with a final stage of digital clipping. Essentially, PI-CFR scheme detects the peaks of the incoming high PAPR signal at the fraction of the sampling rate and for each peak above the clipping threshold, a corresponding "whole" signal of the same magnitude but with its phase reversed is generated. The generated signal is then used to cancel the detected peak signal.

A typical PI-CFR system would contain a number of detection and cancellation (PDC) stages with limited number of pulse generators. Peak re-growth can still happen in the process due to simultaneous application of multiple PDC stages.

Peak Cancellation CFR (PC-CFR)
PC-CFR technique provides CF reduction in somewhat similar to NS-CFR. However, unlike the NS-CFR alluded to earlier, in PC-CFR scheme the regenerated spectrally shaped signal is based on peak samples, this is then used to subtract the original peak signal above the clipping threshold, after suitable delay processing. Whereas for the case of NS-CFR, all the clipped noise samples are filtered and used for subtraction of the corresponding original delayed peak signal. As a result of the simplified approach of only using peak samples for subtraction, it offers less distortion as well as soldering less computational burden.

In each PC-CFR stage, it could contain up to four CPGs (Cancellation Pulse Generator) and with peak scaling involving complex scaling. Another advantage of the PC-CFR scheme is the flexibility it offers, namely it can support multiple air interface standards on the same system by suitably changing the filter used to generate the pulse.

Figure 2 illustrates the plot of the CCDF for the CFR input and output at 7 percent EVM operating point and for six non-adjacent TD-SCDMA carriers over a 15MHz bandwidth with a gain of 3dB at 1E-4. The simulation is done based on an output sampling rate of 76.8MSPS (The PC-CFR Reference Design can also be applied to 61.44MSPS DFE solution.).

Figure 3 depicts PSD performance with Spectrum Emission Mask (SEM) superimposed for the similar configuration. Figure 4 shows forth the performance comparison between PC-CFR, NSCFR and PW-CFR.

Table 1 shows the FPGA resources requirement for a 2 Iteration PC-CFR.

Table 2 provides the resource utilisation required for a 10MHz six-carrier three-antenna (6C3A) TDSCDMA 76.8MSPS [1] Digital Front End (DFE) example with each antenna requiring a two-iteration PC-CFR module. This configuration can be applied to both basestation as well as remote radio unit (RRU).

Based on Table 2 data, using two V4SX35 FPGAs would allow a designer to build a complete 6C6A DFE solution with CFR provision that offers higher efficiency RFPA operation. This is crucial, especially in the context of RRU operation where conduction cooling is required.

CONCLUSION
From the above, it can be seen that PC-CFR scheme is a clear winner as it offers better performance when compared to other known schemes as well as offering low FPGA resource utilisation. These coupled with the availability of compatible TDSCDMA DFE reference design allows RRU or basestation developers short time-to-market and eventual success.

REFERENCES
1. MAC-EXFR-21-029-01.02, January 2007, "TD-SCDMA Digital Front-End Design Description", http://www.xilinx.com

2. Xilinx Application Note XAPP921c, March 2, 2007, "High Density WCDMA Digital Front End Reference Design", http://www.xilinx.com

3. Xilinx Application Note XAPP1033, "Peak Cancellation Crest Factor Reduction Reference Design", http://www.xilinx.com

4. Van Nee, R., and R. Prasad, "OFDM for Wireless Multimedia Communications", Norwood, MA, Artech House, 1999

5. Roland Sperlich, "Adaptive Power Amplifier Linearization by Digital Pre-Distortion with Narrowband Feedback using Genetic Algorithms", PhD Thesis, 2005

6. Olli Vaananen, "Digital Modulators with Crest Factor Reduction Techniques", PhD Thesis, 2006


CAPTIONS
Figure 1: Relationship between Input Power Back Off (IPBO) and Output Power Back Off (OPBO).

Figure 2: CCDF for six non-adjacent TD-SCDMA carriers over 15MHz.

Figure 3: PSD of CFR input and output with two iterations for PC-CFR.

Figure 4: Performance comparison of the various schemes for TD-SCDMA at 76.8MSPS.

Table 1: Resource Utilisation Summary for Two-Iteration PC-CFR Design (Virtex-4)

Table 2. Resource Utilisation Summary for a 6C3A subsystem with PC-CFR

Click here for Illustrations:

Figure 1, Figure 2, Figure 3, Figure 4, Table 1, Table 2