Xilinx's Virtex-5 FXT FPGAs Feature Highest Performance Embedded Processing Block

(Product News, 4 Apr 2008)

With two industry-standard PowerPC 440 processor blocks, Xilinx Inc.'s Virtex-5 FXT devices deliver high performance while enabling designers to reduce system costs, board space and component count. The Virtex-5 FXT devices are said to be the industry's first FPGAs with embedded PowerPC 440 processor blocks, high-speed RocketIO GTX transceivers and dedicated XtremeDSP processing capabilities. Comprising the fourth platform in the 65nm Virtex-5 family, the Virtex-5 FXT devices deliver the ultimate system integration platform for applications in: wired and wireless communications, audio/video broadcast equipment, military, aerospace, industrial systems, and many others.

Each processor block, with integrated 32kB instruction and 32kB data caches, delivers up to 1,100 DMIPS at 550MHz. Tightly coupled to the PowerPC440 blocks is a new integrated 5x2 cross bar processor interconnect architecture that provides simultaneous access to I/O and memory. Highly integrated, this innovative interconnect architecture includes dedicated master and slave processor local bus interfaces, four DMA ports with separate transmit and receive channels, and a dedicated memory bus interface enabling high-performance, low latency point-to-point connectivity.

Designers can rapidly and easily implement advanced scalable embedded processing applications using the PowerPC 440 embedded processor blocks. The advanced PLB architecture maximizes data transfers between the processor, crossbar and soft IP logic with high-throughput 128-bit interfaces to help minimize system bottlenecks. Also, the enhanced high-performance Auxiliary Processor Control Unit (APU) provides added connectivity for dedicated co-processing engines or custom user defined instructions in applications such as video processing, 3D data processing and floating-point math.

The Virtex-5 FXT platform also integrates high-performance, low-power RocketIO GTX transceivers capable of supporting data rates from 500Mbps to 6.5Gbps. Customers can design applications supporting standards such as XAUI, Fibre Channel, SONET, Serial RapidIO, PCI Express 1.1 and 2.0, Interlaken, and others. Consuming less than 200mW typical power per channel at 6.5Gbps, the GTX transceivers come with many advanced features such as 4-tap DFE receiver equalization in addition to linear equalization and transmit pre-emphasis to improve signal integrity at higher line rates. The new transceiver blocks also include a unique multi-code physical coding sublayer to support both 64B/66B and 64B/67B encoding/decoding schemes saving thousands of logic cells for each channel. In addition, cross-platform pin compatibility enables customers who have designs targeting Virtex-5 LXT and SXT devices to migrate their designs to Virtex-5 FXT devices in order to take advantage of the higher-performance embedded processing and serial connectivity.

The Virtex-5 FXT platform includes up to 384 DSP slices and 16.5MB of internal memory that can be configured to provide over 190 GMACs of DSP processing performance and 92Tbps of memory bandwidth respectively at 500MHz.

The Virtex-5 FXT FPGA platform is supported by the new ISE Design Suite 10.1 development tools from Xilinx. This includes access to all the domain specific tools to streamline complete system designs for logic, embedded and DSP applications. This includes ISE Foundation, Embedded Development Kit (EDK), System Generator for DSP, AccelDSP synthesis tool, ChipScope Pro and ChipScope Pro serial I/O Toolkit, PlanAhead design and analysis tool and ISE simulator.

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