FPGAs Adapt to Ever-changing Broadcast Video Landscape

By: Tim Hemken, Xilinx Inc.
( 1 Mar 2008 )

The serial digital interface (SDI) protocol for transporting uncompressed standard definition video evolved when broadcast studios wanted to convert from analog audio and video to digital audio and video without replacing the enormous coaxial transmission cable infrastructure. Today, the ever-increasing screen resolutions and associated data rates have spawned new serial data communication formats with the same goal of coax reuse.

The first such standard for SDI, authored by the Society of Motion Picture and Television Engineers (SMPTE), is known as SMPTE 259M, commercialized in 1989. At its introduction, the primary chips used for the interface were provided by application-specific standard product (ASSP) chip makers. The data rate for SDI is nominally 270Mbps, adequate for standard definition television (SDTV) resolutions.

In 2002, Xilinx announced the immediate availability of Virtex-II Pro FPGAs. The feature set of this device included multi-gigabit transceivers (MGTs) capable of operating at bit rates as fast as 3.125Gbps. About the same time, the broadcast studios were starting their adoption of the new high-definition television (HDTV) standards with greater screen resolutions and higher data-rate requirements. SMPTE authored a standard known as SMPTE 292M, supporting the serial transmission of uncompressed HDTV video content at a nominal rate of 1.5Gbps, known as HD-SDI.

Xilinx Senior Staff Applications Engineer John Snow, realizing that the two data rates could be supported by a single Virtex-II Pro MGT, integrated multiple ASSP chips into a single Xilinx FPGA—vastly reducing the cost of these interfaces, especially in video switcher and master controller designs where there are multiple video streams. Snow authored the first application notes for these two interface standards using FPGAs. These application notes included free reference designs written in Verilog and VHDL source code. The code and documentation allowed broadcast system engineers to easily implement fully featured SDI and HD-SDI receivers and transmitters and other associated functions, such as video test pattern generators, in Virtex-II Pro FPGAs.

The acceptance of HDTV among the masses continues to grow. This amazing technology brings viewers closer to reality and, as a result, the amount of HD content is increasing. Today, HD-capable receivers are achieving mass-market price points and consumers are buying HDTVs at accelerating rates. The multi-rate SDI and HD-SDI reference designs are increasingly important for distributing digital audio and video content inside the broadcast studio.

Today, the SMPTE organization is not standing still. They consistently publish new standards to handle video formats that require higher bandwidth. Two of the latest standards are known as dual-link HD-SDI (SMPTE 372M) and 3G-SDI (SMPTE 424M and SMPTE 425M), both providing 3Gbps of total bandwidth.

The dual-link HD-SDI standard uses two HDSDI rate links combined together to facilitate the transfer of richer color (more pixel color data) or faster update rates (1,080 lines at a 60-Hz progressive frame rate as opposed to a 30-Hz frame rate). The two coax cables forming a dual-link HDSDI interface can be replaced with a single coax cable using 3G-SDI.

An example of an application requiring the increased data rates is driven by the cinema business as it migrates to digital data. Digital cinema standards use 36 bits of data per video sample, compared to the 20 bits per sample typically used by HDTV formats. The increased number of bits per video sample coupled with higher screen resolutions results in market demand for digital interfaces running at 3Gbps.

Even within a single SMPTE standard there are opportunities for FPGA "future proofing". 3G-SDI is actually defined by two standards: SMPTE 424M and SMPTE 425M. SMPTE 424M defines the physical and electrical characteristics of the serial interface itself. SMPTE 425M defines how to map various video formats to the interface. Even though it was only published in 2006, SMPTE is already at work modifying SMPTE 425M to accommodate additional video formats.

A FEW EMERGING APPLICATIONS THAT USE HD-SDI FOR VIDEO CONNECTIVITY

CCD Cameras
Ultra high-speed, high-sensitivity broadcast cameras capable of capturing clear, smooth, slow-motion video—even in limited lighting—are extremely useful for recording events such as professional baseball games played at night. These cameras can capture fast-moving phenomena that cannot be perceived clearly with the naked eye, such as the footage of a ball's impact with a bat. Showing these events in slow-motion video improves the viewer experience significantly.

The CCD (charge-coupled device) camera shown in Figure 1 uses an FPGA to perform signal synthesis processing and color processing, as well as interfacing to the CCD driver. The CCD driver in turn drives the CCD, mechanical shutter control, and trigger control.

The incoming video signal is converted to digital format by the analog-to-digital converter and then stored in off-chip memory. When the data transfer for an entire frame is complete, the data from the memory is synthesized by the FPGA and sent over the network using HD-SDI. The processing time required from trigger to HD-SDI output is one second or less. The FPGA also controls the memory and the ADC.

Video over IP
Some video production centers are starting to use Ethernet to transmit crystal-clear HD streams across the network. Images are pre- and post-processed to enhance picture quality in real time with low latency and then transported over the network using various encoding and decoding standards (codecs). The data must be compressed, as the stream size and rate are very high.

For example, a transmission of 1,920x1,080 pixels at 30fps requires a data rate of 1.5Gbps uncompressed. Add to that multiple channels and the rate goes even higher.

Application-optimized FPGAs with embedded DSP blocks, on- and off-chip memories, abundant logic to build bridging functions, and Ethernet and HD-SDI connectivity are the ideal solutions to build such systems.

Figure 2 shows a block diagram of a video over IP system. The FPGA reads the data presented over an HD-SDI link and then processes it. A codec, such as H.264, is used to compress the data. The data is then converted into Ethernet packets with the appropriate header information for decoding at the receiving end and finally sent over Ethernet links using a MAC.

HDTV Picture Quality Monitor
Previously, consumers could access high-quality video and multi-channel audio through DVDs only. As HD broadcasts become commonplace, comparisons with DVDs are natural. As a result, viewers are more aware of picture quality, particularly for HD.

Picture quality is likely to become a major differentiator between service providers. Picture quality monitors for objective and subjective testing of picture quality in conjunction with perceptible error measurements are now required.

Real-Time HD AVC
Advanced video coding (AVC) is a video compression technique used to deliver video at half the required bit rates. AVC was first used with standard-definition videos, but is even more compelling for HD service providers.

AVC achieves its most significant gains over MPEG-2 through substantial improvements to the motion-compensated prediction process. It doubles the accuracy of motion prediction, uses smaller block sizes to allow objects to be tracked more accurately, and has many more reference frames to search for a good motion-predictive match. Thus, a real-time high-definition AVC video encoder can deliver broadcast-image quality at half the bandwidth of MPEG-2.

FPGAs perform the computationally intensive motion estimation task (Figure 3). Motion estimation is performed using the repeated sum of absolute difference calculations. The data comparisons are very repetitive and many of the calculations are reused. CPU-based implementations tend to struggle to feed the arithmetic logic units from cache; FPGA designs can be customized to retain all of the values in a custom register pipeline.

CONCLUSION
FPGAs have enormous amounts of logic and offer ASIC-like levels of performance. They pack in all of the features that broadcast equipment designers want:
- embedded low-power transceivers capable of supporting several standards such as SDI, HD-SDI, dual-link HD-SDI, 3G-SDI, DVB-ASI, AES digital audio, Ethernet, and PCI Express;
- high-speed DSP blocks;
- embedded processors;
- ethernet MACs;
- PCI Express cores; and
- many video IP cores

By designing video connectivity applications in FPGA products, broadcast equipment manufacturers can lower costs, differentiate their products from the competition, and lower the inherent risk caused by changing standards.

About the Author
Tim Hemken is the Marketing Director at Xilinx Inc., www.xilinx.com. His email is themken@xilinx.com.

Click here for Illustrations:

Figure 1, Figure 2, Figure 3