Reducing Cell Phone Receiver Desense Problems through Design

By: John Whalen, Fairchild Semiconductor
( 1 Mar 2008 )

Serialization interface technologies that utilize differential signalling can reduce the spectral harmonic content by design in many handset applications. The primary mechanism is due to increased harmonic spacing as a result of frequency multiplication. This reduced harmonic content, can result in both lower cost and smaller handset designs because of the reduced requirements for resistive and capacitive filter networks on each data line.

TODAY'S HANDSET DESIGN REQUIREMENTS
The ultra-compact design of today's handsets results in highly sensitive electronic components placed to extreme proximity to one another due to market requirements. In addition, these electronic components must not only be extremely small, but also must not intrude into the operation nor corrupt adjacent devices.

In addition, today's handset designs must operate without flaw with extremely small signal strengths transmitted from the basestation. Often, these signal strengths at the handset can be as low as -110dBm. This necessitates the need for ultra quiet component operation within the handset itself.

PARALLEL INTERFACE DESIGNS
Most handset designs send large amounts of data between the base and to the display through 16-bit microcontroller interface or 8- or 16-bit RGB style interface with data rates from 3MHz to 15MHz. In addition, most handsets now employ one or two cameras that are 8-bit RGB style interfaces that range from 15MHz on up to support CMOS or CCD image sensors.

Often, this bus interface can traverse a 10cm flex circuit in addition to several centimeters on the baseband and several centimeters to the flip or slider. The flex circuits must be designed to withstand hundreds of thousands of bend cycles, achieve a low cost and accommodate dozens of signals that may cross each other to provide the necessary connectivity between base and flip or slider.

The combination length of these flexes and poor impedance control can result in significant signal radiation. The radiation is resultant of both high dv/dt and signal-ended large magnitude voltages. Simply put, the higher the edge rate, the greater the voltage magnitude; and in turn, the greater the emissions.

There are many modelling tools available today that can approximate this emission. Clock sources can easily achieve signal levels of -60dBm or greater, well above the signal strength within the handset receiver.

THE RECEIVER DESENSE PROBLEM: BASESTATION
When the signals inside the handset exceed the signal strengths from the base station, these results in the receiver hearing the larger internal noise source over the weaker signal. As an example, this phenomena, can result of the dropping an important call from a good friend or business associate.

Because the internal noise can be so large, often dozens of channels can be blocked within the handset, rendering it unusable. Handset designers utilize many techniques to minimize this very common phenomenon. These include solutions such as adding a shield across the flex over all wires; or adding low pass filters (series resistor and parallel capacitors) on each data line. Each of these solutions adds cost, and increase size, all of which are counter to the needs of the market and delays new product introduction.

A CLOSER LOOK AT HARMONICS FOR A PARALLEL LCD INTERFACE
A very common LCD interface from a baseband to a slider can be a 16-bit microcontroller interface operating at 5MHz. From an emissions perspective, a 5MHz interface will have harmonics spaced at odd intervals to infinity. These harmonics contain less energy as a function of frequency and at some point become negligible in terms of intrusion. However, the odd harmonic content in a CDMA or GSM band, can be large enough to cause receiver desense, and significant loss of channel utilization.

Figure 1 is a spectrum analyzer plot of a CDMA band with harmonics associated with a phone with out filtering. This particular phone model has had the filter networks removed, and shielding removed from the flex circuit.

A REDUCED HARMONIC CONTENT SOLUTION BY DESIGN
There is a technology that has been recently adapted to the requirements of handset design. This is high speed bus serialization, whereby the 16 data bits and control signals are transformed from a relatively high speed, low voltage differential style interface between base and slider or flip.

HOW SERIALIZATION WORKS IN A TYPICAL APPLICATION
Commonly, a CDMA 5MHz 16 data bit plus control interface bus will be supported with a 19.2MHz baseband clock. A typical SerDes solution includes a phased locked loop (PLL) to speed up and synchronize the parallel to high speed serial data into far fewer wires.

It is critical to recognize, that the reduced wire high speed serial interface is now through the PCB and through the Flex circuit, the harmonic content will now emanate from the odd harmonics from the fundamental high speed serial interface. The original parallel signal traverses an extremely short distance from the baseband to the Serializer and from the Deserializer to the display.

A typical SerDes will reference the 19.2Mhz CDMA baseband clock, multiply it by 13, for a fundamental low voltage differential serial interface of 249.6Mhz. Under these common assumptions, the 3rd and 5th harmonics are respectively 748.8Mhz and 1.248GHz—completely outside the CDMA band.

In addition, the magnitude of the harmonics is smaller because of the lower voltage swing and the differential signaling—that results in a cancellation of the magnetic (radiated) fields. Figure 2 is a spectrum analyzer capture of a serialized solution in a CDMA band.

CORRECT SERIALIZER SELECTION IS ESSENTIAL
Because the fundamental frequency of the serial stream is largely the designer's choice, it is advantageous to select a multiplier within a serializer, which is both high enough to result in large spacing between harmonics, and also such that the harmonics do not land in the middle of a band.

If the designer were to choose a PLL multiplier of 6 or 7 with a 19.2Mhz clock, a 7th harmonic can be placed at the potentially troublesome 806.4Mhz or middle of band 940.8Mhz.

CAMERA INTERFACES
The problem of harmonic generation with a camera interface can be more severe with an LCD. Most microcontroller interfaces utilize generally non periodic signals such as address, chip select and write enable, while a camera has a periodic pixel clock signal. This highly periodic, single-ended LVCMOS level signal emanates a distinct signature that can often interfere with normal handset receiver operation. This is even more notable because camera pixel clock speeds can easily be 40MHz.

To sustain this higher pixel clock speed, edge rates must also be increased, resulting in an even greater level of radiation. Camera interfaces can especially benefit from the harmonic control resulting from serialization

SUMMARY
A choice to serialize has been widely regarded as a value-added proposition to handset designers. This value traditionally has been associated with the large number of wires reduced in a flex circuit, and associated connectors, improved reliability, elimination of voltage translators and ESD components.

It is only recently that handset designers have discovered that serialization also can better improve the electromagnetic compatibility (EMC) within a handset.

This recent discovery has allowed handset designers to achieve smaller form factors handsets in addition to speeding time to market by eliminating printed circuit board (PCB) design cycles needed to accommodate last minute filter networks and shielding.


About the Author
John Whalen is the senior applications engineering manager of the Signal Path group at Fairchild Semiconductor, www.fairchildsemi.com.

Click here for Illustrations:

Figure 1, Figure 2