Atheros' Advanced Bluetooth 2.1 + EDR Silicon Integrates Azuro's PowerCentric

(Product News, 25 Jan 2008)

Atheros Communications Inc., a developer of advanced wireless solutions, has successfully produced working silicon on a single chip Bluetooth 2.1 + EDR design for high-performance mobile and embedded wireless products using Azuro Inc.'s PowerCentric.

Atheros' design was already aggressively clock gated using front-end RTL synthesis tools in addition to containing multiple levels of hand-crafted clock gating logic. By utilizing PowerCentric, Atheros was able to generate superior quality clock trees, reduce post-CTS design flow iterations, and achieve 20 percent reduction in total chip power consumption without any impact on chip size or performance.

Azuro's PowerCentric is a complete replacement for CTS and post-CTS optimization. Unlike traditional CTS solutions, PowerCentric's unique multi-objective algorithm directly considers power, congestion, and timing across multiple modes and corners during the clock tree buffering process. By combining this multi-objective algorithm with advanced logic path timing and placement optimization methods, PowerCentric is able to deliver ultra-low power clock structures without impacting design speed or area, even for the most complex SoC designs.

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