Digital Front End Solution for China's 3G TD-SCDMA Standard

( 1 Nov 2007 )

By Wilson Oon, PHD SMIE, Xilinx Asia Pacific Pte Ltd; and Tim James, David Kenyon, and Sam Chalmers, Multiple Access Communications Ltd


China's Third Generation home grown cellular standard known as Time Division Synchronous Code Division Multiple Access (TD-SCDMA) is one of the two accepted 3GPP time division cellular standards, the other being TDCDMA. The TD-SCDMA standard differs from its counterpart in having a lower chip-rate and having time synchronous transmission on the uplink. Much investment has been poured into this standard and with many successful trials and trial networks installed to-date it is expected that TD-SCDMA networks will be deployed soon after the 3G licenses in China are issued.

DISTINCTIVE SYSTEM FEATURES OF TD-SCDMA
The TD-SCDMA system has been designed with inherent support for two distinctive features. Firstly, given the time synchronous nature of its uplink transmission, an advanced signal processing technique known as joint-detection can be applied for recovery of each user's transmission at the base station. Using joint-detection, the intracellular interference from other users in the same cell can be eliminated fully, leading to higher capacity compared to other asynchronous matched detection techniques. The second distinctive feature is the use of adaptive beam forming for SNR enhancement and interference reduction.

The focus of this article is on a cost-effective FPGA based solution for the TD-SCDMA digital front-end (DFE). The use of adaptive beam forming requires the use of multiple antennas at the base station, with typically between six and eight antennas. On the downlink, each carrier within a sector needs to be routed to each antenna after suitable phase and amplitude weighting and up-conversion. On the uplink, the signal received at each antenna needs to be down-converted to baseband. Up- and down-conversion functions are split between the analogue and digital domains; in the digital domain these functions are performed by the digital up-converter (DUC) and digital down-converter (DDC), which together form the DFE. A generic depiction of the analog and digital front-end of a base station is shown in Figure 1.

Considering the use of a six antennas and six carriers per sector configuration, a total of 36 channels would be required per sector; this typically translates to a large numbers of ASSPs, which can be expensive both in terms of power consumption and PCB area, not to mention reliability issues. This paper describes how a FPGA based DFE solution can be designed and implemented based on an optimized and pre-verified Xilinx System Generator for DSP TDSCDMA DFE library developed on behalf of Xilinx by Multiple Access Communications Ltd.

TD-SCDMA DFE SOLUTION
Subject to specific requirements of sampling rate and tuning span a DFE solution encompassing both the DUC and DDC components can be implemented on a Xilinx FPGA with a highly efficient resource utilization. The DFE library based on Xilinx's System Generator for DSP tool allows for fast and easy reconfiguration, implementation and verification for different antenna and carrier configuration requirements. This is achieved without having to redesign or modify the fundamental components of the DUC and DDC chains, thus allowing the users to cope with the complexity of a DFE design for the base station.

The TD-SCDMA DFE library includes all the necessary System Generator IP blocks to create the DUC and DDC chains, including filter blocks, local oscillator and mixer blocks and various input and output formatting blocks. The DFE library is part of a reference design package which also includes an 18-channel example design for hardware cosimulation, Matlab test scripts implementing 3GPP compliance tests and a full-speed demo solution running on the Nallatech V4 XtremeDSP kit. Figure 2 and Figure 3 show the details of the DUC and DDC signal paths as implemented by the IP blocks from the TD-SCDMA DFE library. The fundamental blocks in the library are the optimized six-channel DUC and DDC blocks, both with a tuning span of 9.6 MHz and an IF sample rate of 76.8 Msps. Baseband data are input and output at the chip rate. The signal path has been carefully designed to achieve optimal resource efficiency and uses a 307.2 MHz system clock. This level of performance is made possible by exploiting the features of the DSP48s available in the V4 SX FPGA.

An example showing the core of a six-channel DUC constructed using the DFE library blocks is shown in Figure 4. Most of the signal processing is performed within the six-channel "TD-SCDMA DUC (6 Channels)" block. The "Local Oscillator" and "DUC Mixer" library blocks are added to allow the composite output of the DUC to be translated from zero to a more practical IF. This subsystem generates the output for a single antenna. Multi-antenna systems can be supported simply by duplicating this subsystem as appropriate. So, supporting an arbitrary number of antennas is relatively straightforward. What about designs that require fewer than six carriers? To use a "full" six-carrier design in such circumstances, although a perfectly valid solution, would lead to an unnecessary large FPGA design. In the worst case, this might prevent the use of a smaller device and hence increase the cost of the solution greatly.

Solutions that require the user to manually remove any unnecessary logic or that involve the implementation and supply of a complete set of pre-defined variants clearly defeat the purpose of the library, which is to distance the user from needing to understand the intricacies of the design. Instead the DFE library has been implemented with some subtle additional logic that helps the downstream design tools optimise away unused logic at build time. Thus, the user simply terminates unused inputs using a library block provided for the purpose. In the three-channel DUC design (Figure 5), Channels 3 to 6 have been tied off using the "Unused BB Input" block, and the control inputs for these channels, which are no longer required, are tied to constant values. Now, although this design is constructed using the six-channel DUC subsystem, all the logic, BRAM and DSP48s dedicated to the unused channels will be removed at build time.

There is a similar story for the DDC. An example six-channel, single antenna design is shown in Figure 6, with a three-channel variant shown in Figure 7. With the DDC, unused channels are optimised away simply by terminating the unused outputs (using standard "Terminator" Simulink blocks) and tying unused control ports tied to constant values. As with the DUC, multiple antennas can be supported simply by duplicating the single-antenna design.

The above description assumes that the tuning span of 9.6 MHz is sufficient, for application requiring a tuning span of greater than 9.6 MHz, two similar DUC or DDC blocks could be cascaded to expand the tuning range to cover, say, 15 MHz.

3GPP COMPLIANCE TESTS AND PERFORMANCE VERIFICATION
As mentioned earlier, the IP blocks in the TDSCDMA DFE library block set are designed to comply with the necessary 3GPP requirements found in TS25.105. As such, the library user can be certain that the implemented DFE system will meet the relevant 3GPP requirements, such as spectrum mask and adjacent-channel leakage ratio (ACLR), for any configuration based on the library, with sufficient margin to allow for the distorting effects of the analogue components.

A summary of the performance with respect to the 3GPP requirements is given in Table 1. 3GPP compliance tests for both the DUC and DDC functions are implemented as Matlab scripts that use hardware co-simulation targets running on the Nallatech V4 XtremeDSP Kit. Figure 8 to Figure 10 show some of the test plots that are generated by the Matlab test scripts, covering the DUC spectrum mask, DDS performance and DDC adjacent channel selectivity and blocking tests.

Further practical tests were also conducted using the V4 XtremeDSP Kit running a fullspeed 12-channel design. This design was used to generate an output signal on an IF in the region of 19.2 MHz using the 14-bit DAC included on the V4 board. The DAC output was fed into an Agilent spectrum analyzer (Figure 11).

The 12-channel design comes with a GUI (Figure 12). The GUI enables various features to be exercised. For example, the DUC output can be fed back into the DDC either via the DAC-ADC route or internally, down-converted and displayed one of the GUI windows.

IMPLEMENTATION RESULTS
As described above, various DFE configurations, ranging from single-carrier, single-antenna to six-carrier, multiple-antenna configurations, can be configured and implemented using the TD-SCDMA DFE library; the only limitation being the FPGA resources available. Table 2 summarizes the FPGA resources required for a half-sector implementation of a six-carrier, three-antenna configuration, while Table 3 shows the resources required for a half-sector implementation of a three-carrier, four-antenna configuration. In other words, processing for a full sector for either scenario could be implemented using just two SX25 devices. Both examples have an IF bandwidth of 9.6 MHz.

CONCLUSIONS
Due to the beam forming requirement in the TDSCDMA standard, a large number of DUC and DDC channels are required for a base station. This paper had shown that quick, efficient and 3GPPcompliant DFE solutions for TD-SCDMA can be realized using the Xilinx V4 SX FPGA and the Xilinx TD-SCDMA DFE library, thus enabling equipment vendors to concentrate on their own product differentiators and shortening the time to market.

Click here for Illustrations:

Figure 1, Figure 2, Figure 3, Figure 4, Figure 5, Figure 6, Figure 7, Figure 8, Figure 9, Figure 10, Figure 11, Figure 12, Table 1, Table 2, Table 3