3D, Multi-gate Transistor Structures for Next Gen Wireless Devices

By: BY ERNEST WORTHMAN, Editorial Director
( 1 Oct 2005 )

It’s no secret that our thirst for ultrawide bandwidth, feature-rich wireless interconnect devices are taxing the limits of current bi-polar transistor technology.

To that end, the last few years have seen development of transistors with three gates and 3D geometries. Many semiconductor designers on the bleeding edge of development believe that such devices will replace today’s devices before this decade’s out.

Wireless devices capable of handling TV, voice recognition, or even containing a universal language translator require semiconductor components with densities much higher and footprints much smaller than what is in production today. As well, such features will require these ICs to run much faster than today’s devices.

To this end, the semiconductor industry has on its radar screen three-dimensional, multi-gate transistor structures. These 21st century electronic switches are smaller, faster and more tightly packed on ICs than planar, single-gate structures that have dominated the transistor footprint of the past two decades.

All That Glitters Isn’t Necessarily Gold
The nagging problem with increasing gate counts, switching speeds and chips that have numbers per chip in the billions is current. Linearly, smaller, more densely packed structures require more current. However, more current causes more heat. The argument can be made that newer designs will require less current per transistor.

However, practicality has shown that the proportionality isn’t necessarily linear. For example, doubling the gate count usually doesn’t inversely reduce the current so both sides of the equation remains balanced. While on-currents may be easier to control it’s theleakage currents in the off states that generally increase, causing power consumption to be driven to unacceptable levels.


Where is the Bleeding Edge?
Since the introduction of these multigate transistors a couple of years ago, today’s state-of-the-art is something called a MuGFET. These devices are based on SOI engineered substrates. Furthermore, the latest device has a 45 nm node MuGFET using 248 nm lithography.

Another device on the edge, although several years old, is the FinFET transistor, the latest of which is processed with 193 nm lithography.

MuGFET is a new, non-planar CMOS transistor architecture keeping pace with Moore’s Law and the requirements set forth by the ITRS 2003, Emerging Research Devices. MuGFETs are potential candidates to replace planar MOSFETs for specific applications in the 32 nm node due to their excellent control of short channel effects, improved current density and improved gate control compared to conventionally scaled transistors, and, consequently, better intrinsic scalability.

MuGFETs are the prime candidates for improving device performance by minimize current leakage when transistors are off. Major semiconductor manufacturers are beginning to examine such innovative transistor structures for designs that are being considered for device technology nodes at 32 nm and shorter. If manufacturability is proven, MuGFETs could eventually replace conventional CMOS transistors. This new technology relies heavily on the use of high quality, very thin SOI wafers as a starting material.

MuGFETS for Memory Density
One of the areas that is in dire need of density improvements is electronic memory. And this area is being studied closely as an emerging market for MuGFET technology. Some work has been done in SRAMs. One notable design is being worked on is from IMEC in Belgium. IMEC’s device is a fully working 6-transistor SRAM cell with an area of only 0.314 mm2.

The MuGFETs implemented in the SRAM cell distinguish themselves by a tall fin of 70 nm, 40 nm higher than typically reported so far, resulting in an increased current density. The transistors have a physical gate length of 40 and 35 nm wide fins. A NiSi source/drain has been used to lower access resistance and a Cu/low-k (Black Diamond) metallization finishes the cell.

RET allowed the patterning of fins, gates and contact holes with 150 nm pitch. The cell layout has been optimized, taking into account the different reticle (phase shift mask) technologies, illumination
possibilities (Quasar or Dipole) and optical proximity corrections for each critical layer. Only uni-
directional patterns are used, leading to a truly lithography-friendly design.

MuGFETs promise a platform breakthrough in IC density, speed and footprint by offering devices with billions and tens of billions of transistors in a small, low power chip. Prototypes are working but GAis still a few years out (likely near the end of the decade). However, if the demand for broadband heats up, we may see these devices a bit sooner.

Analog Switches
Vishay Intertechnology releases a family of analog switches designed for direct battery operation in portable applications. Offering low on-resistance and low-level logic control through the full voltage range of 1.6 to 4.3 V, the switches are aimed at end products including cellphones, set-top boxes, PDAs and media players.

These analog switches can switch both audio and low-voltage power in portable applications. The devices support continuous currents up to 300 mA for Reed Relay replacement and load switching. All products offer bi-directional signal flow and rail-to-rail signal swing. A choice of multiple configurations—including double-pole/double-throw (DPDT), single- pole/double-throw (SPDT), and single-pole/single-throw (SPST)—provides flexibility to the designers of set-top boxes, video games, and medical and industrial applications. Vishay Intertechnology,Inc.



Linear Regulator Controller
Maxim introduces the MAX8737, a dual, high-power, linear-regulator controller used with external n-channel MOSFETs to generate two independent low-voltage supplies for notebook computers. The regulator delivers low output voltages from 0.5 to 2.5 V, and the external MOSFETsallow scalable current design with highly regulated (1%) loads up to 5 A. The MAX8737 operates from a low input voltage, which also reduces the power dissipation in the external n-channel MOSFETs. An external resistive divider is used to fold back the current limit,thereby reducing the overall power dissipation. An output undervoltage timeout is included for low-cost applications that omit the current-sense resistor. The MAX8737 is screened for the extended-industrial temperature range (–40° to +85° C), and is available in a small, 16-pin, 4 x 4 mm TQFN package. Maxim Integrated Products



Security-Enabled Processors
Applied Micro Circuits introduces a low-power, security-enabled 400 series PowerPC processors — the 440GRx and 440EPx. Both processors include an optional integrated security accelerator or Turbo Security Engine, designed to provide Internet Protocol Security (IPSEC) and Secure Socket Layer (SSL) acceleration in support of over 500 Mb/s bandwidth. Targeted at networking applications, the 440GRx processor offers clock speeds up to 667 MHz, with a superscalar architecture that can execute two instructions per clock cycle. With the addition of a high -performance double precision Floating Point Unit and hi-speed USB 2.0 host/device functionality with integrated PHY, the 440EPx is a suitable solution for a range of pervasive applications including printing/imaging, wireless access, industrial control and many digital data and media processing applications.

Both processors feature a 64-bit DDR I or DDR II SDRAM controller with optional ECC protection, a 32-bit PCI 2.2 compliant interface, dual Gigabit Ethernet MACs, four UARTs, one Serial Communications Port, two IIC units, a NAND-Flash controller, general purpose I/Os and programmable interrupt control. Applied Micro Circuits Corp.



OTP Antifuse
PolarFab offers a one-time programmable (OTP) antifuse for PBC4, its 0.5 µm BCD (bipolar-CMOS-DMOS)process. The antifuse is a non-volatile memory element that requires no additional mask layers, allowing for a cost-effective post-package or wafer-level trim capability. The antifuse hard macro is organized in an 8-bit (1B) block, where each individual bit may be selected for programming. In addition, multiple antifuse blocks can be implemented in a single design yielding a greater number of trim bits per die and enabling trim coverage over a wider range or to a greater resolution. PolarFab

Single Chip RFIC
Metalink introduces a family of products, WLANPlus, that will enable IEEE 802.11n networks to deliver the necessary performance and coverage to handle highbandwidth digital entertainment content. The company’s initial product for this market segment is a single-chip RF device to support multiple-input multiple-output (MIMO) antenna technology used in the IEEE 802.11n standard being developed for next-generation Wi-Fi. Metalink integrates two transmit and receive RF chains on one Real- MIMO chip (2 x 2 MIMO). The MtW8150 device features two complete and independent transmit and receive RF chains on a single device, and is designed to be compliant with any IEEE 802.11n standard that is ratified. Operating in the 4.9 to 5.9 GHz frequency range, it supports the pre-standard IEEE 802.11n specification and also can operate on the 20 MHz frequency channel to maintain legacy interoperability. Metalink Ltd.

Seven.Five Now Ready for 4G
Comarco
Wireless Test Solutions latest processor module expands the capabilities of the Seven.Five system to meet the high-speed data requirements for testing cellular networks worldwide utilizing the latest generations of handsets and data cards. Since it is downward compatible with all existing Seven.Five systems installed worldwide, it can be added to those systems to enhance their capabilities.

HiSilicon Collaborates with Cadence and SMIC to Produce Communications Device Cadence Design Systems and Semiconductor Manufacturing International Corporation (SMIC) have announced that HiSilicon Technologies has successfully produced a high-performance communications device using the Cadence Encounter digital IC design platform and targeted at SMIC’s process. In addition, Cadence and SMIC are now making available to mutual customers a digital reference flow that includes support for low power requirements.

The market for digital consumer devices is expanding, creating a demand for powerful and energy-efficient SoCs. With the Encounter platform, HiSilicon, formerly Huawei Technologies’ ASIC Design Center, reduced its risks in timing closure, signal integrity (SI) and design-for-manufacturing (DFM). HiSilicon achieved maximized quality of silicon (QoS) through improved area, performance and power after wires, and realized a fast route to silicon for its communications device.

With its ongoing collaboration with Cadence and SMIC, HiSilicon can optimize its design, software development and system capabilities, enabling it to compete aggressively in the fast-growing communications market.

The SMIC and Cadence digital reference flow kit is available to SMIC customers. SMIC customers may request the reference flow by contacting SMIC’s Design Services at design_services@smics.com.
HiSilicon Technologies