RISC Processor Core

( 1 Jul 2006 )

Cambridge Consultants’ 16-bit RISC microprocessor IP core features a modern, high performance RISC architecture with low gate count, low power consumption and high code density. It is optimized for use in cost- and performance-sensitive ASIC designs. On a 0.18μ CMOS fabrication process, XAP4 can deliver up to 63 Dhrystone MIPS at a clock frequency of 117MHz. The device has both 16-bit data and address buses and is capable of running programs up to 64kb. The first implementation of the processor has a two-stage pipelined Von Neumann architecture. It is delivered to licensees as a soft IP core in Verilog RTL that can be synthesized in as few as 12k gates for ASICs where die size and power consumption must be as small as possible. The processor core includes Cambridge Consultants’ SIF debug logic, which provides full control over the processor and access to its debug registers, together with non-invasive access to any part of the processor’s memory map for data acquisition while a system is running. Cambridge Consultants.