Optimization of Sub-100 nm Γ-gate Si-MOSFETs for RF Applications

By: BY MAYANK GUPTA, V. VIDYA, V. RAMGOPAL RAO, KUN H. TO AND JASON C.S. WOO
( 1 Apr 2006 )

By the end of the twentieth century, the world had seen an explosion in the breadth and depth of applications and devices within the wireless industry. With the increasing popularity of wireless communication systems like cordless phones, wireless modems and personal communication networks, higher levels of RF component integrations are required to reduce both the size and the cost of wireless products.

While CMOS has been the dominating technology for baseband chipsets, the latest evolution in CMOS technology, with shorter channels and faster devices, has made MOSFET a viable choice for RF applications, especially for the frequency in the low GHz region². CMOS technology is attractive because of the low cost, high integration and the maturity of the technology.





However, gate resistance in aggressively scaled CMOS technologies must be taken into account and modeled correctly for accurate benchmarking of such CMOS technologies for RF applications^3-5.
The Gate Parameters
For optimized RF performance, the gate resistance has to be low, even when the gate areas are small. R_g consists of two parts, the distributed gate electrode resistance (R_geltd) and the distributed channel resistance as seen from the gate (R_gch), as shown in Figure 1,4 and given by:




As the MOSFET gate dimensions are reduced, the effective gate resistance increases. Larger gate resistance can substantially degrade the RF high speed performance.

The two figures of merit used for high-speed circuits are the ft and the f_max. These represent the frequencies at which current and power gain, respectively, are extrapolated to fall to unity. For the MOSFET these are defined by:





Where C_gs, C_gd and gm are the gate-to-source capacitance, gate-to-drain capacitance and transconductance, respectively. The power unity gain frequency fmax can be roughly expressed as:



where R_g is the gate resistance.

To reduce the gate resistance, currently, various silicides are being investigated. The problem with this technique is that, as the line width is reduced below 100 nm, due to lack of nucleation sites in the C-49 to C-54 structure of silicides, the sheet resistance increases.6 Even with Co silicides, which are found to be independent of the line width even below 100 nm, the problem of increased gate resistance, due to smaller dimensions still persists.7 This article discusses the authors’ studies on the RF performance of the Γ-gate MOSFET.

The process simulation was done in TSUPREM4 and the device simulations were done in MEDICI, after which the simulated device’s electrical characteristics were matched with the actual results. For various stack lengths, the important RF parameters such as scattering (s-) parameters, forward current gain (H21), unilateral transducer gain G_tumax, ft and f_max were extracted. From the frequency response of different Γ-gate MOSFETs, the best-suited extension length for the Γ-gate MOSFET is predicted.




Fabrication
After LOCOS, a 230 nm poly-Si was deposited on top of 25 nm (PSG) and 1.5 nm of SiO2. The V_th adjust implant was performed by Indium and Boron. A gate oxide of 2.7 nm thickness was then grown. The poly-Si spacer was then formed by the deposition of 58 nm of undoped poly-Si, followed by RIE etchback. A LATI was then done with Phosphorous, at 70°C to shorten the drain extension length. The source extension was doped with Antimony. After the LTO spacer formation, S/D and poly-Si gate implant were performed. The final samples were annealed at 950°C for 15 to 20 seconds. The spacer gate and the dummy stack are connected by a standard two-step Ti silicide process as shown in Figure 1. For further details of the gamma gate MOSFET fabrication, please see (1).












Characterization and Simulations
The structure was simulated in the process simulator TSUPREM4. The I/V characteristics of the device, both experimental and simulated are shown in Figures 3 and 4. Considering the novel fabrication process involving the solid phase diffusion, and the 60 nm gate length, one can see a reasonable match between the simulated and the experimental results. The simulated device had a Vth of 0.53 V while the fabricated device had a V_th of 0.51 V.

The experimental Ion at Vd = 1.0 V and the simulated value of Ion at the same voltage were found to be 0.23 mA/μm and 0.28 mA/μm, respectively at Vd = 0.5 V. Various devices were simulated with dummy stack lengths, and for each stack length the electrical parameters were extracted in the MEDICI device simulator.


Results and Discussion
The s-parameters of the Γ-gate n-MOSFET can be found by defining the input and output port as the gate and the drain respectively.8,9 The device is biased at a Vg of 1V and a Vd of 1V and an AC signal of 0.1V with varying frequency is applied to the gate of the n-MOSFET. To evaluate the device performance at high frequency, two criterions were used: the forward current gain |H21| and the unilateral transducer gain G_tumax, as given by:



The results of simulations are included in Figures 5 and 6. With the extracted s-parameters, ft, the cutoff frequency was calculated and plotted. The |H21| method extracts ft by plotting the |H21| vs. f in the log-scale, the resulting plot is then curve fit by linear regression. The slope m and the intercept c of this fit are used to calculate ft using:



The H21 method assumes that the rolloff of the |H21|, in the |H21| vs. f plot, is –20 dB.2 As can be clearly seen in Figures 5 and 6, the RF performance of the n-MOSFET degrades with an increase in the stack length, since ft falls from 2.53 X 1010 Hz, for the 200 nm stack to 1.38 X 1010 Hz, for the 1000 nm stack. Also, from the figures it is evident that the 240 nm-stack length has a higher ft at 2.80 X 1010 Hz. The plot of G_tumax vs. f also shows a similar trend. It can therefore be concluded that the Γ-gate MOSFET would have the best performance for stack lengths of around 240 nm, where the drain resistance is still under control.

It can be seen from Figure 7 that, as the drain extension of the Γ-gate increases in length, the RF performance of the n-MOSFET degrades. This implies that for Γ-gate n-MOSFETs, smaller stack lengths would certainly perform better than longer stack lengths in the high frequency regime. Yet this does not mean that the reduction in the gate resistance has no effect on the MOSFET, in fact as the small signal model of the MOSFET suggests, the gate resistance would certainly affect the ft. A better measure of the efficacy of the Γ-gate MOSFET would be its comparison with a standard 60 nm MOSFET with the gate length of 60 nm, which would bring out the effect of the increased gate resistance.

For the simulated device, the value of G_tumax was calculated using s-parameters from Equation 5. The result of the simulations is given in Figure 6. The plot of G_tumax vs. f again shows the trend predicted before: for longer stack length the RF performance of the Γ-gate MOSFET is degraded and the value of f_max falls from a figure above 100 GHz to 70 GHz.


Device Stability
While the variations in s-parameters cannot give a clear picture of whether performance varies with the stack length, the stability of the MOSFET is definitely affected. The stability factor, K and the s-matrix, Δ, were calculated from the s-parameters with Equations 7 and 8, and checked against the conditions listed in Equation 9 to determine stability for an amplifier. The equations for this are:



Both K and |Δ| for devices of different stack length, at various frequencies, are plotted in Figures 8 and 9, respectively. The |Δ| vs. f curves were below |Δ| =1 line for all the stack lengths, and they decreased monotonically with increasing frequencies. However, the K vs. f curves increased monotonically, and actually shifted to the left with increasing stack length. This shift implies that devices with long stack lengths meet the conditions of stability at a lower frequency than their short stack-length counterparts.


Conclusion
The Γ-gate n-MOSFET offers the advantage of reduced gate resistance due to the large gate area, while the scaled conventional MOSFET performance is degraded due to a reduction in gate dimensions, with the resulting higher gate resistance. The optimal stack length for the gamma gate MOSFET has been identified in this work from simulations.

It has been found that though the devices with longer stack reach stability at a lower frequency, yet stack length of the order of 240 nm and less would be ideal for GHz range when factors like forward current gain and unilateral current gain are taken in to consideration.


WD&D
References
1. Kun H. To, et al. IEEE Electron Dev.Lett., Feb 2000.

2. Wing Suen and Prof. M. Jamal Deen.”Hot-Carrier Effect on RFCharacteriza-tion of NMOSFET,” Ph.D. Thesis, McMaster University,Canada. Dec.1998.

3. Amitava Chatterjee, et al. IEEE Tran. On Electron Devices, Vol.45, No.6.June 1998 pp.1247-1262.

4. X. Jin, et al. IEDM Tech. Dig , (1998), p. 961.

5. Christian Gunselmann, et al. Proceedings of the IEEE Congress 2000, 2000.

6. Kittle, J.A., et al. Thin Solid Films, 1998, pp.110-121.

7. J.A. Kittle, et al. Thin Solid Films, 1998, pp.404-411.

8. Reinhold Ludwig and Pavel Bretchko. “RF Circuit Design, Theory And Applications,” Pearson Education Asia, 2000.

9. Thomas H. Lee “The Design of CMOS Radio-Frequency Integrated Circuits,” Cambridge University Press, April 1998.