Power-Optimizing Your Telecom Applications

By: By Kevin Cackovic, Altera Corp., and Thomas Rasmussen, TPACK A/S
( 1 Sep 2009 )

Most telecommunications carriers today target a 20 percent power reduction per year on the equipment they deploy. This is in response to increasing power consumption in central offices, which is due to higher bandwidth capacities, increasing linecard port densities, more intelligent processing requirements, and more complex chip implementations. Higher power consumption equals higher operating costs for telecom providers and leads to more complex engineering challenges for equipment suppliers dealing with thermal management.

Semiconductors are a significant part of this power problem. The answer is rethinking chip implementations and delivery in order to meet the aggressive power-reduction goals set by carriers. The key enablers are the latest generation of FPGAs. By adopting the latest manufacturing processes based on 40nm geometries along with innovative approaches to optimize these complex devices, designers can integrate more functionality on a single device while reducing the overall power consumption.

Taking advantage of power reduction provides carrier-Ethernet chip solutions, like the ones offered by TPACK, based on high-performance FPGAs, such as Altera's Stratix IV family. The combination of these FPGAs with power optimizations and highly integrated devices result in a compelling proposition to system vendors. Not only do they continue to meet demands for higher bandwidth capacity and more intelligent processing, but they do so using chip solutions that provide lower power consumption.

Additionally, these chip solutions can be ported to the latest FPGAs reducing power even further. The net result is system implementations that offer lower power consumption. Meeting these strict power efficiency requirements is a major challenge for system developers. Reducing power consumption by 20 percent is not trivial as power consumption continues to increase.

SYSTEM PERSPECTIVE
One major source of system power consumption is the semiconductor devices used to process traffic and the associated memories. For Internet protocol (IP) routing that requires large table lookups and large memories, four to eight ternary content-addressable memories (TCAMs) are required. Because TCAMs typically consume 15W, a total power consumption of 120W is possible.

System developers address this issue by using more dedicated processors and performing more operations at layer 2 and 2.5, using Ethernet and MPLS to avoid TCAMs. DRAM and SRAM memories can be used instead, typically consuming only 2W each. The processors that take advantage of low-power memories then become the major source of power consumption, based on the complexity and bandwidth of the chips involved.

SEMICONDUCTOR ECONOMICS
As the complexity and capacity of chip solutions increase to 100Gbps-based systems, the solution for addressing power consumption is aggressively pursuing the latest advances in semiconductor manufacturing processes. This enables higher density, higher bandwidth devices, and systems with relatively lower power consumption. However, the cost of developing chips at lower geometries increases exponentially with each step down in process geometry (Figure 1). This makes a challenging business case for specialized devices addressing high-end telecom systems.

The number of systems and chips required in high-end telecom systems are measured in the thousands. The many competing protocols and approaches fragment this market even further, making it difficult to predict revenue streams for new chip development. This unpredictability has already discouraged many ASSP suppliers from migrating from 130nm to 90nm processes, with few making the move to the 65nm process and beyond.

SILICON PERSPECTIVE
As process geometries shrink, there are variables such as reduced capacitance and voltage that lead to natural decreases in dynamic power consumption. For example, compared to a 65nm process node with the same architecture, the lower voltage (0.9V) of a 40nm process results in a 33 percent reduction of dynamic power, and a 30 percent capacitance reduction further reduces dynamic power.

However, the reduction in dynamic power may be offset by significant increases in power due to static power increasing dramatically on smaller geometries due to various sources of leakage current. In addition, dynamic power may increase due to the greater density and clock frequencies of the smaller geometries. So, building silicon at 40nm and beyond without aggressively designing for power optimizations results in solutions that move the power curve in the wrong direction.

ADDRESSING THE POWER CHALLENGE
Tackling power consumption in advanced silicon technologies involves a variety of approaches, including process, architectural, and design optimizations ─ all utilized for developing power-optimized solutions. A key factor in delivering these power optimizations, called Programmable Power Technology, allows individual logic array blocks (LABs), memory, and digital signal processing (DSP) blocks to selectively turn on power savings based on specific design requirements.

Various techniques are used to optimize Altera’s 40nm FPGAs for power, each with a different balance of benefits and drawbacks:
• Multiple-gate oxide thicknesses (triple oxide) ─ trades static power for speed per transistor
• Multiple-threshold voltages ─ trades static power for speed per transistor
• Low-k inter-metal dielectric ─ reduces dynamic power and increases performance
• Super strained silicon – increases electron and hole mobility by 30 percent and balances between power and performance
• Copper interconnect – increases performance and reduces IR drop

Telecom linecards often make scheduling decisions based on incoming packet traffic. This requires high- performance external memories to buffer the packets while the scheduling decisions are made. Offering dynamic on-chip termination (OCT) to reduce linecard power consumption is a key factor. Dynamic OCT disables parallel termination on write operations, saving static power when writing the packets into memory.

Programmable Power Technology enables every programmable LAB, DSP block, and memory block to deliver high speed or low power, depending on the design requirements. FPGAs not optimized for power contain blocks designed to run at only one speed ─ the highest possible speed ─ to support timing critical paths (as depicted by yellow blocks in Figure 2). Using the Programmable Power Technology, all LABs in the array, except those designated as timing critical, are set to low-power mode (as depicted by blue blocks in Figure 2). With only the timing-critical blocks set to high-speed mode, power dissipation is reduced substantially.

Another key innovation is providing the ability of development software synthesis and place-and-route engine to be power aware. This power reduction method is transparent to designers and enabled through simple compilation settings. The design engineer simply sets the timing constraints as part of the design entry process and synthesizes the design to meet performance. The tools automatically select the required performance for each piece of logic as well as minimizing power through power-aware placement, routing, and clocking.

The resulting design meets the designer’s minimum power requirements. The designer has the option to select low-effort or high-effort optimization. Selecting high-effort offers the greatest power savings at the expense of longer compilation times. Results vary based on design and effort level selected. The goal of this feature is to reduce power without designer intervention while having minimal impact on design performance.

POWER OPTIMIZATION
The power optimization using Quartus II development software occurs in three stages. The first performs a “power-aware” synthesis. Power-aware means that the software can minimize the number of RAM blocks accessed at each clock cycle or re-arrange the design to eliminate high-toggling (or glitch-prone) logic.

Next, a power-aware place and route is used to route signals by minimizing capacitance or by creating power-efficient DSP block configurations is performed. PowerPlay power optimization guides the fitter to optimize the design for power by taking advantage of the power-specific architecture features. Using timing constraints, the software ensures the critical paths in a design are optimized for performance, while non-critical paths are optimized for power instead. This has a positive impact on the core static-power consumption, typically reducing it by up to 37 percent.

By basing chip development on FPGAs rather than on foundry-based manufacturing, it is possible for an application-specific standard product (ASSP) to utilize the latest developments in chip manufacturing to enable power-efficient solutions. This approach is called Softsilicon from TPACK. It uses Stratix IV FPGAs to provide carrier-Ethernet packet-processing, traffic-management, and packet-mapping chip solutions to telecom system vendors.

Softsilicon not only enables the development of new chips with higher capacities, but also reduces the power consumption of existing designs. These carrier packet engines, which provide integrated carrier-Ethernet packet processing and traffic management, are based on various generations of Stratix FPGAs manufactured using different geometries (Figure 3).

By moving from Stratix to Stratix II FPGAs the capacity of the carrier packet engine was increased from 6Gbps to 20Gbps, while decreasing the relative power-per-Gbps switching capacity. However, by porting this solution from Stratix II to Stratix III FPGAs , the power consumption was reduced by up to 40 percent.

The power-consumption advantages provided by the Softsilicon approach are:
• Provides more switching capacity at a relatively lower power per Gbps by adopting the latest FPGA platforms
• Reduces the power consumption of existing designs by porting to the latest FPGA platforms

With Softsilicon, a real alternative to ASSPs is provided that enables better performance, especially in relation to power consumption. Integration also plays a part, as the ability to integrate more into a single chip ensures lower real-estate requirements and lower power consumption. Additionally, the flexibility to update the solution and fix errors quickly if needed is offered. It is important to note that the disadvantage of ASSP integration is that the risk of errors increases with complexity, while with FPGAs, these errors can be corrected quickly, minimizing the risks of integration.

There are power consumption advantages to using Softsilicon products in system design. However, it provides even more power-saving potential if a universal linecard approach to system design is adopted. Figure 4 shows the possibilities that can be implemented.

A universal linecard, or multi-function linecard, is based on Softsilicon and pluggable optics that allow different interfaces and logic to be defined. This allows a single linecard hardware design to be used for multiple applications. For example, in one application, the linecard supports Ethernet over NG-SONET/SDH packet mapping, while in another application it supports carrier Ethernet switching and traffic management. All that is required is a linecard design prepared for the various options to support and a number of Softsilicon FPGA images that programs the underlying FPGA platform during power-up.

ADVANTAGES OF THE UNIVERSAL LINECARD APPROACH
The universal linecard approach results in many system-development advantages. From a power perspective, the most important is reducing the number of defined functions on the card at deployment. In a typical chip development, all of the potential feature and interface options that system vendors and their carrier customers might require are designed into the chip.

By adopting a universal linecard approach, only the features that are required for the particular deployment need to be loaded into the FPGA. This means fewer features, less logic, a smaller FPGA, and lower power consumption. This approach requires managing a number of FPGA image variants, but allows accommodation of carrier-specific requirements.

While the power-consumption reduction requirements of carriers seem daunting, meeting power optimization requirements is possible. High-performance FPGAs, Softsilicon, and a universal linecard approach to system design provide all the ingredients needed to not only meet, but probably exceed customer demands, while also enabling differentiation, responsiveness, and fast time-to-market with higher capacity packet-transport solutions.

Click here for the illustrations:

Figure 1, Figure 2, Figure 3, Figure 4