Power Amplifier Design for WiMAX Application

By: By Richard Wang and Bill Chang
( 1 Mar 2009 )

This article will describe a classical architecture of a power amplifier design for WiMAX application, as well as explain the function and theorem of each block in the said architecture. This will also introduce the design philosophy about how to select the semiconductor materials and the RF parameters in each stage based on three-stage GaAs HBT power amplifier design, as well as explain the design methodology. Apart from this, the article also intends to introduce the “back-off” concept and how and why this is needed for power amplifier design.

WIMAX POWER AMPLIFIER ARCHITECTURE
The power amplifier is a key component in both 802.11d-2004 and 802.11e-2005 WiMAX systems. Its function is to amplify the power energy of the RF signal from the transceiver, which comes from baseband with OFDMA modulation. The power amplifier would then transmit this energy to an antenna, which in turn would radiate this energy to free space.

The basic block would include a GaAs HBT power amplifier, power detector circuitry, voltage bias control, temperature sensor and programmable attenuator.

GaAs HBT power amplifier: amplifies the RF signal linearly without bringing in any distortion.

Power detector circuitry: includes the coupler, which gets the output power strength, and transfers this coupled power to a certain degree of voltage or power, and then feedback to either transceiver or baseband.

Bias control: to supply the bias voltage of GaAs HBT power amplifier in some certain degree, the designer can also add the bias control to change the bias to improve the efficiency.

Temperature sensor: the power amplifier would generate a lot heat when the output is high power. The temperature would shift the RF performance a little bit, so we need to know what the temperature is and feedback that message to the system for further calibration for the RF performance.

Attenuator: this scalable attenuator would allow implementation of the power control mode for the power amplifier. In general, there are two options for this attenuation implementation: one is to add a real tunable attenuator and the other is just to turn off the interstage power amplifier and bypass the signal.

CIRCUIT DESIGN
Silicon CMOS, Silicon Bi-CMOS, SiGe Bi-CMOS/HBT and GaAs HBT are the most popular processes today. RF CMOS is getting more mature and has been used in many wireless systems and standards. As for cellular devices, most transceivers today are based on the RF CMOS process. However, the power amplifier design is still dominated by GaAs HBT.

There are some disadvantages to design CMOS PAs, for example, the efficiency, isolation, breakdown voltage, noise, etc. In order to achieve same RF characteristic by using CMOS, the designer may need to design an even more complicated architecture. Therefore most PA designs still use the GaAs HBT process.

GaAs HBT
Base on the specifications and performance requirement, designers normally use three stages for power amplifier design. Figure 2 show the regular block diagram of a three-stage GaAs HBT power amplifier design. Min and Mout are the input matching and output matching, respectively, M12 and M23 are the interstage matching.

The main target for first stage is not to amplify the power and gain; instead, the first stage needs to reduce the noise as much as it could. The concept is the same as that of a low-noise amplifier. Therefore first stage is the key factor for noise level. Figure 3 is an example that explains how it works.

In formula 2, IIP3 is the interception point of third harmonic with linear gain, Pin is the input power, and Pout is the output power. P_IM3 is the power level of third harmonic.

From Formula 1, we find that the Noise Figure for the first stage dominates the cascaded noise figure. So if we want to reduce the total noise figure, we have to make sure the noise figure in the first stage is the lowest. Hence, we have to optimize the noise performance for the first stage power amplifier. From Formula 2, IIP3 total is dominated by IIP3 from first stage. So we have to optimize the IIP3 design to make sure we could achieve the linearity as much as possible.

There are a of lot design considerations for noise figure optimization, here we choose to have a bigger emitter area. Base on the simulation result, we found the noise figure is better if the emitter area is bigger. From Figure 4, the noise figure is 4.2 at 2GHz if the emitter area is 270µm square; while the noise figure would be 3.8 at 2GHz if the emitter area is around 405µm square.

There are several methods to improve the linearity; one of the most used methods is “back-off” (Figure 5). The P1dB is the power level that is 1dB away from the power level of linear gain over Pin. The back-off means to reduce the power a little bit to have the signal within the linear region. The more complicated modulation would need more linear dynamic area and then need more power back-off.

One popular way to back-off the power is by controlling the bias—not driving the power amplifier to saturation area region but still keeping it working in the linear region. As what is indicated in Figure 5, the maximum power would be confined in P_back-off. There is another way to confine the output power by lowering the input power level, but the designer has to make sure the multi-stage amplifier has enough gain to drive the power to desired level. Figure 6 and Figure 7 show the IMD3 performance at different power levels, respectively. The IMD3 will improve when the power is backed off; however, the designer has to make sure the output power meets the product specification.

The power back-off, however, would degrade the efficiency of the power amplifier; there is a trade-off between power efficiency and linearity, and that’s what the designer has to make up for in reference to the product specification.

The design principle of the second stage amplifier is to keep amplifying the signal while keeping it as linear as possible, and making sure the power level is high enough to drive the final stage power amplifier. So the design philosophy of second stage power amplifier is amplifying the signal linearly.

The design purpose of the final stage is fully amplifying the power level. To meet the product specification, the designer may use parallel designs to add the power from several power amplifier bank (Figure 8). In practice, the designer has to consider the power characteristics of GaAs and also to save the design area. Therefore the designer would use several power amplifier banks to make sure the power level meet the product specification. Figure 9 shows what the power amplifier bank is and how to connect them parallel.

CONCLUSION
GaAs HBT has very good isolation characteristics, efficiency, performance and lower noise figure compared to the CMOS process, so it is a good choice for high power and high linearity WiMAX power amplifier designs. The three-stage design would make sure the power amplifier could drive the low-level signal (normally less than 0dBm from the transceiver) to higher levels. Also, the power back-off design can be implemented to make sure the signal level will meet the linearity specifications of the WiMAX 16 QAM.


About the Author
Richard Wang is the Director of Sales, APAC, for Wavesat. He holds an M.S. degree from the National Chiao-Tung University in 1995.


CAPTIONS
Figure 1: Block diagram of a typical power amplifier design.
Figure 2: The regular block diagram of a three-stage GaAs HBT power amplifier.
Figure 3: Three-stage HBT power amplifier.
Figure 4: Noise figure comparison based on different emitter areas.
Figure 5: Power back-off design method.
Figure 6: Simulation result of IMD3 amplifier working on the condition of P1dB.
Figure 7: Simulation result of IMD3 amplifier based on the working condition of P_Back-Off
Figure 8: Power amplifier with multiple transistors paralleled.
Figure 9: Sets of power amplifiers with paralleled transistors.

Click here for the illustrations:

Figure 1, Figure 2, Figure 3, Figure 4, Figure 5, Figure 6, Figure 7, Figure 8, Figure 9