Advancing Automatic Test Equipment Depends on High-performance Switches

By: By Mark Schrepferman, Peregrine Semiconductor
( 1 Mar 2009 )

High-performance RFICs push the limits of the “state of the art” in the automatic test equipment (ATE) that is used to develop them. To satisfy this delicate balance, the test equipment must be able to evaluate the limits of the IC under development. The problem, then, becomes circular, because making better RFICs requires better ATE, and better ATE requires better RFICs. The good news is that each IC advancement enables the next generation of development for test equipment, and visa versa.

Used in many of the important circuits in test equipment, the single-pole, double-throw (SPDT) RF switch remains a critical component in the overall performance of high-end ATE designs. For example, switches are used for selecting filter banks (Figure 1), for building high-performance digital step attenuators (DSAs; Figure 2), for routing the RF signal path, as well as many other important functions.

Because their performance is so vital, the materials used to manufacture switches are regularly under scrutiny as performance needs and bandwidth for ATE change. For instance, the switching characteristics of gallium arsenide (GaAs) and silicon-germanium (SiGe) limit their ability to provide repeatable switching performance in ATE applications across a wide frequency range. So, as bandwidth needs grow, test equipment manufacturers are now looking at highly-reliable CMOS semiconductor technology to improve performance. Compared to GaAs or SiGe, silicon-based devices offer the benefits of fast settling times, broadband performance, insertion loss, manufacturing precision, industry-leading electrostatic discharge (ESD) performance, and control logic.

SETTLING TIME
Typical GaAs-based switches demonstrate gate lag in settling time (see Figure 3), which causes both phase and insertion loss drift. This is a problem because fast settling time is one of the most important specifications for ATE. SPDTs with fast settling times enable faster measurements, which lead to increased throughput, better usability, and reduced manufacturing test costs. In a market where ATE manufacturers are looking for a point of difference, providing these improvements can lead to competitive product advantages.

To develop state-of-the-art equipment, ATE manufacturers generally specify switch insertion loss to be within 0.05dBm in 20µs. The more rapidly a switch settles to within this limit, the faster the ATE can report a measurement.

Figure 3 shows a typical GaAs MESFET switch with a final settling time of 83µs with approximately 1dB overshoot after a switching event. (Overshoot means that the transient power can be 26% higher than the final power consumption for a given switch. The transient power will be even higher when multiple switches are used.) Since they began using GaAs MESFET switches, ATE engineers have had to compensate for these transients in their designs. Unfortunately, the transient settling time in GaAs high-performance switches is unpredictable, making these switches more complex to use in ATE.

A switch with a fast settling time and no overshoot, therefore, could significantly improve performance. The PE42552 UltraCMOS switch from Peregrine Semiconductor, for instance, settles to within 0.05dBm insertion loss within 13µs as shown in Figure 4. Note that this beats the ATE manufacturer specification by 7µs. The switch also has no overshoot, which leads to a lower transient power consumption.

In a DSA, for example, it is important to have accurate signal amplitude and phase, so that the rest of the instrument knows the correct signal level. When switches with a transient settling time delay are used to make DSAs, this delay can translate into errors in the attenuator or the switching function. Using a silicon switch eliminates these design issues. However, meeting the stringent switching specification is challenging even for silicon, and currently, only UltraCMOS silicon-on-sapphire technology (SOS) has demonstrated the ability to meet ATE switching requirements (Figure 4).

BROADBAND PERFORMANCE
ATE designers are looking to develop products that deliver leading-edge testing and measurement across multiple communication protocols. Such an instrument must offer superior broadband performance, and the components inside must also be broadband. High linearity at low frequencies is what drives the ability of a switch to be used as a broadband component. Although many GaAs switches are specified to operate from DC, they typically have a corner frequency of 100MHz. Operating below this corner frequency significantly degrades linearity and introduces noise figure problems.

Any non-linearity from components in test and measurement equipment can also cause intermodulation distortion (IMD), which can inhibit the equipment's ability to provide accurate measurements. The situation is particularly challenging when the linearity of the IC in the ATE is not at least equal to that of the device under test. For this reason, ATE designers demand the best linearity available from components.

Fortunately, designers can use a single switch that offers broadband performance from the kilohertz range to 7.5GHz. For example, the PE42552 SPDT switch operates from 9kHz to 7.5GHz with high linearity across these frequencies, making it a good choice for handling multiple communication protocols (Figure 5). The data in Figure 5 shows that the PE42552 has significantly better low frequency linearity than a GaAs MESFET switch.

INSERTION LOSS
In addition to consistent broadband performance and linearity, insertion loss performance is another important RF parameter for switches used in state-of-the art test equipment. If a signal path has multiple switches, the loss of each switch becomes multiplied. This scenario becomes particularly important in high power paths, where high insertion loss results in higher power consumption. Additionally, insertion loss and noise from switches can limit the dynamic range in a receive path.

Insertion loss is particularly challenging for GaAs switches, because, typically, as linearity is improved, insertion loss and die size suffer. This is because the conventional GaAs circuits need multi-stacked FETs or multi-gate FETs and large gate width to achieve good linearity, which results in large parasitic off-capacitances with degraded insertion loss. In contrast, UltraCMOS technology is composed of a stack of FETs manufactured on a perfectly insulating sapphire substrate, providing the ability to pass high-power RF signals with good linearity without a negative impact on insertion loss or die size.

Figure 6 shows that the typical insertion loss for an UltraCMOS broadband switch is <1dB at 7.5GHz, which is nearly half that of comparable GaAs switches. This lower insertion loss could lead to reduced power consumption, simplified designs, and larger dynamic ranges in ATE.

LOT-TO-LOT PRECISION
Consistently achieving target performance levels requires that ATE manufacturers minimize variations in switch performance from one lot of devices to the next. This type of precision is important because when ATE manufacturers are confident with consistent switch performance from lot to lot, they can eliminate prescreening, increase speed of delivery to market, and remove unnecessary cost. Due to the consistency of silicon processing, CMOS switches provide repeatable performance from lot to lot.

ESD PROTECTION
With a typical Class 0 (<250V) or Class 1A (250V to 500V) HBM ESD rating, GaAs MESFET switches can be damaged by even small electrostatic discharge (ESD) events. This type of damage from ESD can be particularly challenging to detect. In an attempt to avoid it, ATE designers have traditionally added external ESD protection to the GaAs switches. Unfortunately, this external protection can degrade the instrument's overall performance by limiting the power and dynamic range of the circuit.

Silicon technology makes it possible to include ESD protection devices within the silicon switch. For instance, UltraCMOS switches provide class 1C performance on the RF pins (1,000V to 2,000V) HBM. Having ESD protection on the chip not only makes them less susceptible to damage, but it simplifies designs by reducing or eliminating the need for external protection.

CMOS CONTROL LOGIC
A CMOS interface is easier to design into existing or new equipment because logic functions are typically implemented in CMOS. If the switch is also manufactured using a CMOS process, then the chip manufacturer can include logic on chip that works easily with the rest of the design. For example, the PE42552 SPDT switch was designed with integrated CMOS control logic driven by a single-pin, low-voltage CMOS control input. Another way to improve switch functionality is to enable a user-defined logic table. An UltraCMOS switch includes a logic-select pin that inverts the logic polarity for back-to-back switching applications, effectively changing the logic definition of the control pin.

Today’s RF test instrumentation must make extremely accurate and repeatable measurements. With the coming of Long Term Evolution (LTE) mobile phones, mobile WiMAX, and, perhaps, a combination of both, the performance of test and measurement equipment will be pushed to the limit. The good news is that test and measurement suppliers have access to the devices that will allow them to meet their targets. For example, UltraCMOS technology was commercialized years ago; is in high-volume production; and parts are being custom tailored for the ATE marketplace. Devices like these can help ATE manufacturers offer the broadband, repeatable, accurate performance that their customers are demanding.


REFERENCE
Baker, Ray. "CMOS-based Digital Step Attenuator Designs," Wireless Design & Development Magazine, May 2004. http://www.psemi.com/articles/2004/2004_ar_5.pdf

About the Author
Mark Schrepferman is responsible for design and implementation of Peregrine’s UltraCMOS RFIC marketing strategy and business development activities for the Communication and Industrial market segments. Since joining Peregrine in early 2006, Mark has led the company’s focus toward penetrating these markets with its leading-edge product portfolio.

Click here for the illustrations:

Figure 1, Figure 2, Figure 3, Figure 4, Figure 5, Figure 6